Commit fef66348 authored by Gauthier Quesnel's avatar Gauthier Quesnel
Browse files

WIP

parent bca1f3a4
Pipeline #40230 failed with stage
in 60 minutes
......@@ -24,13 +24,17 @@ enum class edge_type : i8
model, component;
};
status
add_model(modeling& m, component& parent, model& mdl);
status
add_component(modeling& m, component& parent, component& comp);
void
destroy_vertice(modeling& m, component& parent, int index);
void
unref_vertice(modeling& m, component& parent, int index);
void
status
add_edge(modeling& m, const port& src, const port& dst);
void
destroy_edge(modeling& m, component& c, int index);
struct edge
......@@ -77,6 +81,6 @@ struct modeling
data_array<model, model_id> models;
};
}
} // namespace irt
#endif
\ No newline at end of file
#endif
......@@ -10,6 +10,47 @@ static void
destroy_model(modeling& m, model& m);
static void
destroy_component(modeling& m, component& c);
static bool
is_input_port_exist(modeling& m, component& parent, int index, i8 port);
static bool
is_output_port_exist(modeling& m, component& parent, int index, i8 port);
status
add_model(modeling& m, component& parent, model& mdl)
{
auto ret = status::success;
auto mdl_id = m.models.get_id(mdl);
if (parent.vertices.can_alloc(1)) {
irt_return_if_bad(parent.vertice.try_emplace_back());
auto& vertice = parent.back();
vertice.id = ordinal(mdl_id);
vectice.type = vertice_type::model;
} else {
ret = status::simulation_not_enough_model;
}
return ret;
}
status
add_component(modeling& m, component& parent, component& comp)
{
auto ret = status::success;
auto comp_id = m.components.get_id(comp);
if (parent.vertices.can_alloc(1)) {
irt_return_if_bad(parent.vertice.try_emplace_back());
auto& vertice = parent.back();
vertice.id = ordinal(comp_id);
vertice.type = vertice_type::component;
com.parent_to(parent.d);
} else {
ret = status::simulation_not_enough_model;
}
return ret;
}
void
destroy_vertice(modeling& m, component& parent, int index)
......@@ -50,6 +91,30 @@ unref_vertice(modeling& m, component& parent, int index)
c.vertices.pop_and_swap(index);
}
status
add_edge(modeling& m,
component& parent,
int index_src,
int index_dst,
i8 port_src,
i8 port_dst)
{
irt_assert(index_src >= 0 && index_src < c.vertices.size());
irt_assert(index_dst >= 0 && index_dst < c.vertices.size());
auto ret = status::success;
auto& edge = parent.edges.emplace_back();
edge.src = parent.vertices[index_src].id;
edge.dst = parent.vertices[index_dst].id;
edge.type_src = parent.vertices[index_src].type;
edge.type_dst = parent.vertices[index_dst].type;
edge.port_src = port_src;
edge.port_dst = port_dst;
return ret;
}
void
destroy_edge(modeling& m, component& c, int index)
{
......@@ -92,4 +157,60 @@ destroy_component(modeling& m, component& c)
m.components.free(c);
}
} // namespac eirt
\ No newline at end of file
static bool
is_input_port_exist(modeling& m, component& parent, int index, i8 port)
{
u64 id = parent.vertices[index].id;
bool exist;
if (parent.vertices[index].type == vertice_type::component) {
auto compo_id = to_enum<compo_id>(id);
auto& compo = m.components.try_to_get(compo_id);
exist = 0 <= port && port < compo.x.size();
} else {
auto model_id = to_enum<model_id>(id);
auto& model = m.models.try_to_get(model_id);
exist =
dispatch(model, [port]<typename Dynamics>(Dynamics& dyn) -> bool {
if constexpr (is_detected_v<has_input_port_t, Dynamics>) {
return 0 <= port && port < length(dyn.x);
}
return false;
});
}
return exist;
}
static bool
is_output_port_exist(modeling& m, component& parent, int index, i8 port)
{
u64 id = parent.vertices[index].id;
bool exist;
if (parent.vertices[index].type == vertice_type::component) {
auto compo_id = to_enum<compo_id>(id);
auto& compo = m.components.try_to_get(compo_id);
exist = 0 <= port && port < compo.y.size();
} else {
auto model_id = to_enum<model_id>(id);
auto& model = m.models.try_to_get(model_id);
exist =
dispatch(model, [port]<typename Dynamics>(Dynamics& dyn) -> bool {
if constexpr (is_detected_v<has_output_port_t, Dynamics>) {
return 0 <= port && port < length(dyn.y);
}
return false;
});
}
return exist;
}
} // namespac eirt
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