Commit 2c7912e4 authored by Gauthier Quesnel's avatar Gauthier Quesnel
Browse files

WIP

parent fef66348
Pipeline #40243 failed with stage
in 60 minutes and 1 second
...@@ -24,3 +24,4 @@ AlwaysBreakTemplateDeclarations: true ...@@ -24,3 +24,4 @@ AlwaysBreakTemplateDeclarations: true
# BeforeLambdaBody: false # BeforeLambdaBody: false
SpacesInSquareBrackets: false SpacesInSquareBrackets: false
AllowShortEnumsOnASingleLine: true AllowShortEnumsOnASingleLine: true
AlwaysBreakAfterReturnType: AllDefinitions
\ No newline at end of file
...@@ -24,18 +24,13 @@ enum class edge_type : i8 ...@@ -24,18 +24,13 @@ enum class edge_type : i8
model, component; model, component;
}; };
status status add_model(modeling& m, component& parent, model& mdl);
add_model(modeling& m, component& parent, model& mdl); status add_component(modeling& m, component& parent, component& comp);
status void destroy_vertice(modeling& m, component& parent, int index);
add_component(modeling& m, component& parent, component& comp); void unref_vertice(modeling& m, component& parent, int index);
void status add_edge(modeling& m, const port& src, const port& dst);
destroy_vertice(modeling& m, component& parent, int index); void destroy_edge(modeling& m, component& c, int index);
void status compute_simulation(modeling& m, simulation& sim);
unref_vertice(modeling& m, component& parent, int index);
status
add_edge(modeling& m, const port& src, const port& dst);
void
destroy_edge(modeling& m, component& c, int index);
struct edge struct edge
{ {
......
...@@ -6,14 +6,16 @@ ...@@ -6,14 +6,16 @@
namespace irt { namespace irt {
static void static void destroy_model(modeling& m, model& m);
destroy_model(modeling& m, model& m); static void destroy_component(modeling& m, component& c);
static void static bool is_input_port_exist(modeling& m,
destroy_component(modeling& m, component& c); component& parent,
static bool int index,
is_input_port_exist(modeling& m, component& parent, int index, i8 port); i8 port);
static bool static bool is_output_port_exist(modeling& m,
is_output_port_exist(modeling& m, component& parent, int index, i8 port); component& parent,
int index,
i8 port);
status status
add_model(modeling& m, component& parent, model& mdl) add_model(modeling& m, component& parent, model& mdl)
...@@ -123,6 +125,11 @@ destroy_edge(modeling& m, component& c, int index) ...@@ -123,6 +125,11 @@ destroy_edge(modeling& m, component& c, int index)
c.edges.pop_and_swap(index); c.edges.pop_and_swap(index);
} }
status compute_simulation(modeling& m, simulation& sim)
{
}
static void static void
destroy_model(modeling& m, model& m) destroy_model(modeling& m, model& m)
{ {
......
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